1. Field of the Invention
The present invention relates to a semiconductor device having a superjunction (hereinafter referred to as “SJ”) structure, such as an SJ MOSFET.
2. Description of the Related Art
A conventional SJ MOSFET is manufactured by forming a p-type body layer (base layer) on a substrate having an SJ structure including n-type columns and p-type columns arranged alternately along the surface, and forming an n-type source diffusion layer on the surface of the p-type body layer. When the column is patterned as fine as 2 μm or below, for example, the above-described structure has a limit in fine patterning because the body layer can not be made sufficiently small.
On the other hand, a trench-gate SJ MOSFET is known as a structure suitable for fine patterning. In the case of the trench-gate, positions for formation of n-type columns and p-type columns may deviate from positions for formation of trench-gates along the surface, or etching or the like for formation of trenches may advance deeper than an intended depth and reach the p-type column. In such the cases, a carrier passage can not be formed from the p-type body layer to the n-type column and an overall on-resistance of the semiconductor device is increased as a problem.
With regard to this problem, JP-A 2003-124464 (paragraph 0038, FIG. 1) discloses an SJ MOSFET including an n-type silicon region formed in a region that contains almost the entire of a carrier passage. This carrier passage links the n-type column and the p-type column that cover the bottom of a trench-gate.
Even in the SJ MOSFET disclosed in the above-described document, it is required to form the n-type silicon region in consideration of displacements of the trench along the surface and in the vertical direction. Therefore, the n-type silicon region inevitably has a large width and depth, which ultimately limits fine patterning.